Photodiode arrays or photodiodes are used in an assortment of applications including, but not limited to, radiation detection, optical position encoding, and low light-level imaging, such as night photography, nuclear medical imaging, photon medical imaging, multi-slice computer tomography (CT) imaging, and ballistic photon detection etc. Typically, photodiode arrays may be formed as one- or two-dimensional arrays of aligned photodiodes, or, for optical shaft encoders, a circular or semicircular arrangement of diodes.
Conventional computed tomography (CT) scanners and digital radiography systems use large numbers of X-ray detectors, on the order of several hundred to several thousand, in which each X-ray detector includes a scintillator to convert X-rays into light and a photocell to convert the light into an electrical signal. In such systems, it is preferred that the detectors are high density and that the detectors have equal pitch, i.e. the center-to-center distance from detector to detector is equal. Thus, the detectors are located as close as possible to one another, resulting in a detection system which has a high detection efficiency so that a patient is exposed to only the minimum amount of X-rays required to produce a satisfactory image. As the devices become smaller, however, it becomes more difficult to provide efficient interconnections between devices, thus negating the benefits of the smaller device size.
One conventional method of achieving high-density integration of photodiode arrays is to fabricate devices by implementing a plurality of techniques, including the creation of a pn-junction on one side of the substrate and subsequently routing the connection to the other side of the substrate via reactive ion etching (RIE). This results in the formation of dry etch holes, passivation of the walls of the dry etch holes with oxide, and development of a front-to-back connection, via placement of either a metal line or a doped polysilicon layer within the holes. This method, however, is not cost efficient and also results in low throughput of the device.
In addition, the prior art is replete with attempts to design, fabricate, and implement high-density semiconductor arrays. For example, U.S. Pat. No. 5,501,990, assigned to Motorola, Inc. discloses, “a method of fabricating a high density light emitting diode array with semiconductor interconnects comprising the steps of: providing a substrate of non-conductive material with a major surface, a conductive layer of material on the major surface of the substrate, a first carrier confinement layer on the conductive layer, an active layer on the first carrier confinement layer and a second carrier confinement layer on the active layer; separating portions of the second carrier confinement layer, the active layer and the first carrier confinement layer into a plurality of light emitting diodes positioned in rows and columns and separating the conductive layer into a plurality of columns connecting a first contact of each light emitting diode in a column to a first contact of each other light emitting diode in the column; forming column contacts connected to the conductive layer at an end of each column; and forming a second contact on the cap layer of each light emitting diode and connecting second contacts for each light emitting diode in a row to the second contacts of all other light emitting diodes in the row.”
U.S. Pat. No. 5,656,508, also assigned to Motorola, Inc. discloses, “a method of fabricating a two-dimensional organic light emitting diode array for high density information image manifestation apparatus comprising: providing an electrically insulative substrate with a planar surface; depositing a layer of electrically conductive material on the planar surface of the substrate; patterning the layer of electrically conductive material to form a plurality of laterally spaced, conductive strips defining first electrodes; depositing a layer of dielectric medium on a surface of the conductive strips and the planar surface of the substrate; depositing a layer of photoresist on the layer of dielectric medium; patterning the photoresist using a cavity defining mask to expose portions of the dielectric medium; etching away the exposed portions of the dielectric medium to form a plurality of laterally spaced cavities, each of the plurality of cavities being positioned on an associated one of the defined first electrodes and exposing therein the associated first electrode; striping off the photoresist; depositing in each of the cavities an electroluminescent medium in the successive order of a layer of hole transporting material, a layer of active organic emitter, a layer of electron transporting material and a layer of a low work functional metal; depositing a layer of ambient stable metal on the dielectric medium so as to sealingly overlie each of the cavities and electrically contact the layer of low work function metal in the cavities; and patterning the layer of ambient stable metal into metal strips in a direction orthogonal to the conductive strips so as to define second electrodes sealing each of the plurality of cavities.”
In addition high cost of manufacturing and low throughput, another typical problem with high-density integration of conventional photodiode arrays is the amount and extent of crosstalk that occurs between adjacent detector structures, primarily as a result of minority carrier current between diodes. The problem of crosstalk between diodes becomes even more acute as the size of the photodiode arrays, the size of individual detectors comprising the arrays, the spatial resolution, and the spacing of the photodiodes is reduced.
In certain applications, it is desirable to produce optical detectors having small lateral dimensions and spaced closely together. For example in certain medical applications, it would beneficial to increase the optical resolution of a detector array in order to permit for improved image scans, such as computer tomography scans. However, at conventional doping levels utilized for diode arrays of this type, the diffusion length of minority carriers generated by photon interaction in the semiconductor is in the range of at least many tens of microns, and such minority carriers have the potential to affect signals at diodes away from the region at which the minority carriers were generated. Therefore, the spatial resolution obtainable may be limited by diffusion of the carriers within the semiconductor itself, even if other components of the optical system are optimized and scattered light is reduced.
Various approaches have been used to minimize crosstalk including, but not limited to, providing inactive photodiodes to balance the leakage current and using conventional two-dimensional or three-dimensional structures, such as trenches, moats, or insulating structures between photodiodes or other active devices to provide isolation between the devices.
For example, U.S. Pat. No. 4,904,861, assigned to Agilent Technologies, Inc., discloses “an optical encoder comprising: a plurality of active photodiodes in an array on a semiconductor chip; a code member having alternating areas for alternately illuminating and not illuminating the active photodiodes in response to movement of the code member; means connected to the active photodiodes for measuring current from the active photodiodes; and sufficient inactive photodiode area on the semiconductor chip at each end of the array of active photodiodes to make the leakage current to each end active photodiode of the array substantially equal to the leakage current to an active photodiode remote from an end of the array”. Similarly, U.S. Pat. No. 4,998,013, also assigned to Agilent Technologies, Inc. discloses “means for shielding a photodiode from leakage current comprising: at least one active photodiode on a semiconductor chip; means for measuring current from the active photodiode; a shielding area having a photodiode junction substantially surrounding the active photodiode; and means for biasing the shielding area photodiode junction with either zero bias or reverse bias.”
In addition to manufacturing cost, low throughput, and crosstalk, it is difficult to achieve high density photodiode arrays with uniformity of generated photocurrent and sufficient density of generated photocurrent. The photocurrent may be enhanced by internal gain caused by interaction among ions and photons under the influence of applied fields, such as occurs in an avalanche photodiode (APD). Elsewhere, passivation of photodetectors via sulfidization has repeatedly shown reduction of surface states, thereby reducing dark current density in sequence incrementing photocurrent density.
As mentioned above, as photodiode detector devices become smaller, it becomes more difficult to provide efficient interconnections between devices, thus putting an additional demand on device electrical requirements. The prior art has attempted to manage interconnect density by forming dense metal interconnect patterns, because high-density VLSI and ULSI devices typically require multiple levels of surface metallization in order to accommodate their complex wiring patterns. Multiple level metallization creates planarity problems in the metallization layers, however, thereby limiting interconnection density. Complex process steps are also needed to provide multiple levels of metallization.
For example, U.S. Pat. No. 5,276,955, assigned to Supercomputer Systems Limited Partnership discloses “a method for forming a multilayer substrate having high density area array interconnects, the method comprising the steps of: (a) providing three or more pre-assembled subsections, each subsection comprising: a planar substrate having a pair of generally planar exposed surfaces and being comprised of a dielectric medium having a plurality of conductive layers disposed therein, the conductive layers including: at least one power layer; and at least one X-Y signal pair layer; and a pad layer on at least one of the surfaces of the planar substrate, the pad layer comprising a plurality of metallic interconnect pads disposed on the surface of the planar substrate such that an exposed surface of the interconnect pads is raised above the exposed surface of the dielectric medium surrounding the interconnect pads, each of the interconnect pads being selectively connected to one or more conductive regions in the signal pair layer or the power layer; (b) stacking the three or more pre-assembled subsections together such that the interconnect pads on the pad layer of one subsection align with the interconnect pads on the pad layer of an adjacent subsection; and (c) electrically and mechanically joining the three or more pre-assembled subsections in a simultaneous manner to concurrently form the multilayer substrate by metallurgically bonding the interconnect pads on adjacent subsections without bonding the surrounding dielectric medium.”
Thus, conventional high-density photodiode array manufacturing techniques are costly and have low throughput. More specifically, low-cost manufacturing and test techniques are not compatible with high-density photodiode array designs. Thus, there is a need for a high density photodiode array that can be manufactured at high-throughput and low-cost and that is capable of producing uniform, high-density photocurrent. There is also a need for a high-density semiconductor circuit and an economically, technically, and operationally feasible fabrication method for a photodiode array capable of generating uniform as well as high-density photocurrent.
In addition, there is a need for a front-side illuminated, back-side contact (FSL-BSC) photodiode array having improved characteristics, including high production throughput, low-cost manufacturing via implementation of batch processing techniques; uniform as well as high photocurrent density owing to the presence of a large continuous homogeneous, heavily doped layer; and front to back intrachip connections.
There is also a need for a front-side contact, back-side illuminated (FSC-BSL) photodiode array having improved characteristics, including high production throughput, low-cost manufacturing via implementation of batch processing techniques; uniform as well as high photocurrent density owing to the presence of a large continuous homogeneous, heavily doped layer; and back to front intrachip connections.